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Can this image classifier maintain its intelligence while becoming small enough for the edge?
Can this image classifier maintain its intelligence while becoming small enough for the edge?
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Deploying neural networks and intelligent decision loops on raw silicon targets.
When physical memory is full, which page must be evicted?
Imagine a system running under constraint. Its physical RAM is small, containing only 3 physical frames. Right now, physical memory is completely saturated, filled with three active pages:
$$\text{RAM Frames: } [ \text{Page 2} \ | \ \text{Page 5} \ | \ \text{Page 7} ]$$
A thread executes an instruction requesting virtual address space residing in Page 3.
The MMU looks up the translation in the Page Table, finds it invalid, and raises a Page Fault. The Operating System traps the fault and prepares to copy Page 3 from disk into RAM. But there is a bottleneck: all physical frames are occupied.
To resolve the fault and bring Page 3 into memory, the operating system must choose one page currently in RAM and evict it back to disk.
This decision is known as Page Replacement.
How do we decide which page should leave? The policy we choose determines our system's memory efficiency. Three core algorithms answer this question:
First-In, First-Out (FIFO) "Which Page arrived first?" Evict the oldest page loaded into RAM, regardless of how frequently it is being used.
Least Recently Used (LRU) "Which Page has been unused the longest?" Evict the page that has not been accessed for the longest duration, relying on the principle of temporal locality.
Optimal (OPT) "Which Page will be needed farthest in the future?" Evict the page that will go the longest before being requested again.
See how these three different strategies handle the exact same reference sequence under the same constraint:
$$\text{Reference Sequence: } 1 \rightarrow 2 \rightarrow 3 \rightarrow 1 \rightarrow 4$$
Observe how the exact same access trace produces completely different eviction choices and page fault rates depending on the active policy.
The Optimal policy represents the absolute ceiling of performance, guaranteeing the minimum possible Page Faults for any known reference sequence. However, in practice, a real-world operating system cannot implement the Optimal policy because it cannot know future memory references in advance. Real-world systems must approximate this behavior using historical data, making LRU the standard benchmark for practical implementation.
We have learned how Paging places fixed-size pages into physical frames. We have also learned how Page Replacement decides which page should leave when all frames are occupied.
But notice something important: all of this assumes that memory is being managed as fixed-size pages.
What happens when a program needs memory as a meaningful, variable-sized unit rather than as a collection of equal-sized pages?
What if memory management followed the logical structure of the program itself?
PrajnaEdge is a technology company exploring the space between understanding technology, experimenting with ideas, and turning them into things that can be experienced.
PrajnaEdge began with Embedded Systems — exploring the foundations that connect hardware, software and intelligent computation.
The first technology universe is built around that foundation. The journey will expand as new ideas, experiments and products emerge.
PrajnaEdge is a technology company created by Devaharsha Meesarapu.
I am the engineer behind the design, development, and content of PrajnaEdge. I build low-level systems where code directly controls hardware, bridging the gap between register-level silicon behavior and intelligent edge decision loops.
I am an Embedded Firmware Engineer focused on developing software for resource-constrained systems. My experience spans bare-metal firmware, device drivers, microcontroller peripherals, and communication protocols, working across the boundary between hardware and software.
My work has involved microcontroller-based systems, real-time behaviour, hardware interfaces, and communication technologies such as CAN, CAN FD, UART, SPI, and I²C. I am particularly interested in understanding systems from the lowest level upward—from registers and peripherals to intelligent edge systems.
Engineering is not just about writing code; it is about managing constraints, timings, and physical hardware characteristics. True mastery of complex systems comes from understanding the interactions across different layers of the stack.
This conviction is why I built PrajnaEdge—to bridge the gap between conceptual theory and direct, register-level physical reality.
Software that runs directly on hardware without an operating system.
"Every embedded application begins long before main()."
An Operating System manages hardware and software resources so complex applications can work efficiently.
"When one loop is no longer enough to carry the burden."
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PrajnaEdge is an interactive learning platform designed for systems engineers, developers, and technology enthusiasts. The educational materials, simulation blocks, and visual code tracers are provided for instruction and concept validation. We make no warranty regarding their completeness or applicability to real-world industrial systems.
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